publications.bib

@PHDTHESIS{bregier2007phd,
  author = {Vivian Brégier},
  title = {Synthèse automatisée de circuits asynchrones optimisés prouvés
        quasi insensibles aux délais},
  school = {INP Grenoble},
  year = {2007},
  month = SEP,
  address = {Grenoble, France},
  url = {http://www.are-ata.org/publications/2007_phd_Synthèse_automatisée_de_circuits_asynchrones_optimisés_prouvés_quasi_insensibles_aux_délais.pdf}
}

@INBOOK{folco2005tma,
  author = {Bertrand Folco and Vivian Brégier and Laurent Fesquet and Marc Renaudin},
  title = {Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits},
  volume = {200},
  series = {IFIP International Federation for Information Processing
        Series},
  publisher = {Springer},
  year = {2005}
}

@INPROCEEDINGS{folco2005,
  author = {Bertrand Folco and Vivian Brégier and Laurent Fesquet and Marc Renaudin},
  title = {Synthesis of Area Optimized Quasi Delay Insensitive Circuits},
  booktitle = {System On Chip 2005},
  series = {IFIP International Conference on Very Large Scale Integration},
  year = {2005},
  month = OCT,
  address = {Perth, Australia},
  url = {http://www.are-ata.org/publications/2005_Synthesis_of_Area_Optimized_Quasi_Delay_Insensitive_Circuits.pdf}
}

@INPROCEEDINGS{bregier2004,
  author = {Vivian Brégier and Bertrand Folco and Laurent Fesquet and Marc Renaudin},
  title = {Modeling and synthesis of multi-rail multi-protocol QDI circuits},
  booktitle = {Thirteenth International Workshop on Logic and Synthesis},
  year = {2004},
  month = JUN,
  address = {Temecula, California},
  url = {http://www.are-ata.org/publications/2004_Modeling_and_synthesis_of_multi-rail_multi-protocol_QDI_circuits.pdf}
}

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