| [1] | Vivian Brégier. Synthèse automatisée de circuits asynchrones optimisés prouvés quasi insensibles aux délais. PhD thesis, INP Grenoble, Grenoble, France, September 2007. [ bib | .pdf ] |
| [2] | Bertrand Folco, Vivian Brégier, Laurent Fesquet, and Marc Renaudin. Synthesis of area optimized quasi delay insensitive circuits. In System On Chip 2005, IFIP International Conference on Very Large Scale Integration, Perth, Australia, October 2005. [ bib | .pdf ] |
| [3] | Bertrand Folco, Vivian Brégier, Laurent Fesquet, and Marc Renaudin. Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, volume 200 of IFIP International Federation for Information Processing Series. Springer, 2005. [ bib ] |
| [4] | Vivian Brégier, Bertrand Folco, Laurent Fesquet, and Marc Renaudin. Modeling and synthesis of multi-rail multi-protocol qdi circuits. In Thirteenth International Workshop on Logic and Synthesis, Temecula, California, June 2004. [ bib | .pdf ] |
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